With the advent of the integrated circuit industry, the demand for device density increased becomes a trend. It is essentially to have extra-high density devices in a chip so as to achieve powerful commercial competitiveness. However, as a device scaled from one micron down to submicron or beyond, it may suffer more stringent problems. For examples, hot carriers effect and punchthrough effects are two of the major constraints in CMOS transistor scaling. Further, parasitic resistance and capacitance in the scaled device structure are required to avoid.
Other limiting factor for devices with submicron dimensions is the conductivity of the source/drain regions and the poly-gate. For example, the sheet resistance of diffusion regions increases from 25 .OMEGA./sq - in a 1 .mu.m technology to 50 .OMEGA./sq - in a 0.5 Am technology. A self-aligned silicide technology, namely salicide, involving the formation of silicide on poly-gate, source and drain contact simultaneously. The salicide process can provide not only low-sheet resistance for S/D regions and for gate electrode in MOS devices but also a very clean suicide-silicon interface. Further, it does not require any additional lithography and etching. In addition, the alignment was predetermined.
However, the salicide process requires consuming a portion of silicon substrate while the silicide forming metal reacts with the semiconductor substrate. The silicidation process will countervail the ultra shallow junction formed for scale down devices. Hence, it is desired to have a silicon layer deposit on the source/drain regions for silicidation. To ensure the source/drain region isolate from gate region during CVD deposit silicon layer process, an oxide layer is usually formed before the layer deposited. The processes thus require complex process.
Thus an object of the present invention is to simplify the fabrication process.